US6809666B1 - Circuit and method for gray code to binary conversion - Google Patents

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This is a continuation-in-part of two co-pending U. The present application is related to concurrently filed U. The invention generally relates to image sensor systems; and in particular, the present invention relates to an image sensor utilizing a digital pixel sensor architecture.

Digital photography is one of the most exciting technologies that have emerged in the past years. With the appropriate hardware and software and a little knowledgeanyone binary to gray code conversion truth table pdf put the principles of digital photography to work.

Digital cameras, for example, are on the cutting edge of digital photography. Recent product introductions, technological advancements, and price cuts, along with the emergence of email and the World Wide Web, have helped make digital cameras the hottest new category of consumer electronics products. Digital cameras, however, do not work in the way that traditional film cameras do. In fact, they are more closely related to computer scanners, copiers, or fax machines. The photosensitive device reacts to light reflected from the scene and can translate the strength of that reaction into electronic charging signals that are further digitized.

By passing light through red, green, and blue filters, for example, the reaction can be gauged for each binary to gray code conversion truth table pdf color spectrum. When the readings are combined and evaluated via software, the camera can determine the specific color of each segment of the picture.

Because the image is actually a collection of numeric data, it can easily be downloaded into a computer and manipulated for more artistic effects. Digital cameras, however, do not have the resolution attainable with conventional photography.

While traditional film-based technology, limited only by the granularity of the chemically based film, typically has a resolution of tens of millions of pixels, image sensors for use in most commercially available digital cameras acceptable to general consumers have a resolution of slightly more than one or two million pixels. Although digital cameras having resolutions of up to six million pixels are available, these high-resolution cameras are prohibitively expensive.

Furthermore, the dynamic range of digital image sensors is often not as broad as is capable with film-based conventional photography. Such an image sensor, referred to as a digital pixel sensor DPSprovides a digital output signal at each pixel element representing the light intensity detected by that pixel element. The incorporation of an on-chip memory alleviates the data transmission bottleneck problem associated with the use of an off-chip memory for storage of the pixel data.

In particular, the integration of a memory with a DPS sensor makes feasible the use of multiple sampling for improving the quality of the captured images. Multiple sampling is recognized as the technique capable binary to gray code conversion truth table pdf achieving a wide dynamic range without many of the disadvantages associated with other dynamic range enhancement techniques, such as degradation in signal-to-noise ratio and increased implementation complexity.

The aforementioned patent and patent applications are incorporated herein by reference in their entireties. In the DPS sensor of the ' patent, the analog-to-digital conversion ADC is based on first order sigma delta modulation. While this ADC approach requires fairly simple and robust circuits, it has the disadvantages of producing too much data and suffering from poor low light performance.

The aforementioned patent and patent application are incorporated herein by reference in their entireties. What is needed is a digital image sensor with integrated supporting circuitry for improving the performance of the image sensor.

In accordance with one aspect of the present invention, an image sensor includes a sensor array, a data memory and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene.

The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement. The data memory is in communication with the sensor array and stores the pixel data. The pixel normalization circuit is coupled to the data memory for rearranging the pixel data into a pixel-bit order and providing the rearranged pixel data as output signals.

In accordance with another aspect of the present invention, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The data memory is in communication with the sensor array for storing the pixel data. The pixel normalization circuit is coupled to the data memory for normalizing the pixel data and providing normalized pixel data as output signals.

In one embodiment, the sensor array outputs the pixel data in a sensor-bit arrangement and the pixel normalization circuit includes a pixel rearrangement circuit for rearranging the pixel data into a pixel-bit arrangement.

In another embodiment, the sensor array outputs the pixel data represented in Gray code and the pixel normalization circuit includes a conversion circuit for converting the pixel data into a binary representation. In another embodiment, the data memory stores reset values for each of the pixel elements in the sensor array and the pixel normalization circuit binary to gray code conversion truth table pdf a reset subtract circuit for subtracting the reset values from the pixel data for each of the pixel elements.

In yet another embodiment, the sensor array uses multiple sampling for establishing a wide dynamic range for the sensor array, and the data memory includes a time index memory for storing the time index value for each of the pixel elements. In another embodiment, the pixel normalization circuit includes a multiple sampling normalization circuit for calculating the normalized pixel data for each of the pixel elements based on the pixel data and the time index values.

According to another aspect of the present invention, a method for constructing an n-bit Gray code to binary conversion circuit is described. A method for converting an n-bit Gray code number to an n-bit binary number includes 1 computing the binary value of the least significant bit LSB of the n-bit Gray code number using an XOR tree; the XOR tree including a first set of XOR gates for evaluating the n-bit Gray code number and generating the binary value of the LSB in a shortest gate delay time; 2 determining in the XOR tree a first group of bits, other than the LSB, for which binary values of the first group of bits are also generated; and 3 providing a second set of XOR gates for computing the binary values of a second group of bits of the n-bit Gray code number, other than the first group of bits and the LSB, the second set of XOR gates computing the binary values in a gate delay time less than or equal to the shortest gate binary to gray code conversion truth table pdf time of the XOR tree.

According to yet another aspect of the present invention, a method for converting an n-bit Gray code number to an n-bit binary number includes: The Gray code to binary conversion circuits according to the present invention provides high speed conversion and conserves circuit area.

The present invention is better understood upon consideration of the detailed description below and the accompanying drawings. In the present disclosure, like objects which appear in more than one figure are provided with like reference numerals.

According to the present invention, an image sensor, based on a digital pixel sensor DPS architecture, is integrated binary to gray code conversion truth table pdf a pixel normalization circuit for enhancing the efficiency and the performance of the image sensor.

The pixel normalization circuit in the image sensor of the present invention performs one or more of the pixel normalization functions including pixel-bit rearrangement, Gray code to binary conversion, digital correlated double sampling operation, and multiple sampling normalization operation.

Image sensor may be used in an image capturing device such as a digital camera for capturing stationary or video photography. Image binary to gray code conversion truth table pdf produces digital image data as output signals on bus The image sensor core of image sensor is implemented as a digital pixel sensor DPS array DPS array is a two-dimensional array of light detecting elements, also called photodetectors. For color applications, a mosaic of selectively transmissive filters is superimposed in registration with each of the photodetectors so that a first, second, and third selective group of photodetectors are made to sense three different color ranges, for example, the red, green, and blue ranges of the visible spectrum, respectively.

DPS array generates digital signals as sensor readout on output bus In the present description, a DPS array or a sensor array refers to an image sensor having an array of photodetectors where each photodetector produces a digital output signal. In the present embodiment, DPS array implements the digital pixel sensor architecture described in aforementioned U.

The digital output signals of a DPS array have advantages over the conventional analog signals in that the digital signals can be read out at a much higher speed.

Image sensor further includes an integrated on-chip memory for storing at least one frame of image data from DPS array Thus, memory has the capacity to store pixel data for at least N by M pixels in k-bits.

In the present embodiment, memory also includes additional storage capacity for storing other parameters used by image sensor as will be described in more detail binary to gray code conversion truth table pdf. In one embodiment, DPS array has by pixels in 10 bits and memory has a size of at least 1.

As described in aforementioned patent application Ser. Memory includes a memory location for storing the k-bit pixel data generated by DPS array Memory also includes memory locations and for storing the threshold indicator and the time index information for each pixel when multiple sampling is used as will be described in more detail below.

Furthermore, memory includes a memory location for storing the reset values from each of the pixels in DPS array The reset values are used in a correlated double sampling CDS methodology to eliminate non-uniformity in the sensor array as will be described in more detail below. Memory location is included only when image sensor employs binary to gray code conversion truth table pdf CDS methodology.

In other embodiments, when CDS methodology is not used, memory location is not needed. In operation, an image is focused on DPS array such that a different portion of the focused image impinges on each of the sensor pixels in the array. Each sensor pixel comprises a phototransistor whose conductivity is related to the intensity of light impinging upon the base of the phototransistor.

The analog current through the phototransistor thus corresponds to the intensity of light impinging upon the phototransistor. The serial bit streams, generated over a frame period, is provided on bus as digital output signals representative of the average intensity of light impinging on the phototransistors. In image sensorsensor readout from DPS array binary to gray code conversion truth table pdf provided through a multiple sampling update circuit to memory for storage.

Multiple sampling update logic circuit is used to implement multiple sampling for improving binary to gray code conversion truth table pdf dynamic range of image sensor and will be described in more detail below.

In the case when multiple sampling is not used, sensor readout from DPS array may be coupled directly to memory DPS array provides sensor readout in the form of bit planes. In DPS arraythe photodetectors generate one bit binary to gray code conversion truth table pdf the digital pixel data simultaneously and provide the one bit of digital data as output signals on bus Thus, the first bit of the digital pixel data i.

The photodetectors then generate the next bit of the k-bit pixel data for each sensor pixel and the next bit plane, containing bit 1 of all the pixels, is written to memory as bit plane b for pixel bit 1. The photodetectors of DPS array generate the k bits of digital pixel data successively for each sensor pixel and the data are written to memory as successive bit planes a to p as illustrated in FIG.

Memory location of memory includes storage capacity for storing all of the bit planes for the k-bit binary to gray code conversion truth table pdf pixel data. Because DPS array outputs pixel data in a sensor bit arrangement, binary to gray code conversion truth table pdf pixel data are stored in memory in the form of bit planes. However, the sensor bit arrangement of the pixel data in memory is not useful for applications interfacing with image sensor as the k-bit pixel data for a pixel are scattered throughout memory To provide for a compatible interface with other image processing devices receiving the image captured by image sensorwhat is needed is for the pixel data to be in a pixel bit arrangement, i.

The desired pixel bit arrangement in memory for a 4-bit pixel is illustrated in FIG. The first four bits of memory location stores the 4-bit pixel data of pixel 0which is followed by the 4-bit pixel data of pixel 1 and pixel 2 and so on. That is, it is not important that adjacent pixels are arranged adjacent to each other. For the pixel bit arrangement, it is only important that all the bits for one pixel binary to gray code conversion truth table pdf grouped together in a consecutive bit order.

The order of the pixels can be arranged in any ways which are desirable for the particular application. Therefore, in one embodiment, in the pixel bit arrangement, all bits of pixel 0 is followed by all bits of pixel 3 which is then followed by all bits of pixel 2.

Binary to gray code conversion truth table pdf pixel data stored in memory can be read out by using the proper memory addressing scheme. In accordance with the present invention, a pixel normalization circuit is binary to gray code conversion truth table pdf for performing a pixel rearrangement operation on the pixel data stored in memory Pixel normalization circuit is integrated on the same integrated circuit chip of image sensor The integration of pixel normalization circuit on image sensor improves the speed and performance of image sensor In one embodiment, pixel normalization circuit operates only to rearrange the configuration of the pixel data in memory The rearranged pixel data may be written back to memory so that memory has in storage the desired pixel bit arrangement of an image.

In another embodiment, the rearranged pixel data may simply be outputted on bus to other devices coupled to receive the image data from image sensor and the data in memory are not updated in the pixel bit arrangement. In another embodiment of the present invention, besides pixel rearrangement, pixel normalization circuit includes circuits for performing other normalization functions on the pixel data read out from DPS array The normalization functions can include but is not limited to Gray code conversion, CDS subtract, and multiple sampling normalization.

In those cases, the normalized pixel data in pixel bit arrangement may be written back to memory for storage or outputted on bus

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